a. Field of the Invention
The present invention generally relates to semiconductor manufacturing, and more particularly to the positioning of multiple exposure fields during semiconductor manufacturing.
b. Background of Invention
Within the field of photolithography, the accurate placement of exposed image fields over a semiconductor layer may be of paramount importance, especially since one or more additional layers may subsequently be fabricated over this layer. Intra-layer positioning or field stitching may, therefore, involve the placement of lithographically generated images (i.e., exposed fields) relative to each other over a shared layer of a semiconductor wafer. Thus, in some implementations, multiple semiconductor device (e.g., a processor chip) exposures may be replicated on the semiconductor wafer surface with, for example, some field region overlap.
Accordingly, different techniques associated with positioning each exposed field relative to its adjacent field(s) may be realized using, for example, predetermined pattern images (i.e., petals) located on each of the exposed images. Using metrology tools, the generated predetermined pattern images may be utilized in order to ascertain alignment errors between multiple exposed fields. If these ascertained alignment errors falls outside certain tolerances, a lithographic re-work of the layer may be needed, whereby the patterned photoresist is stripped, another photoresist layer is reapplied, and the fields are lithographically re-exposed on the newly applied photoresist layer.